1. Field of the Invention
The invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device including organic thin film transistors and a method of manufacturing the same, in which a metallic material of pad portions can be prevented from being torn apart and corroded during a packaging process of tape automated bonding (TAB).
2. Discussion of the Related Art
Due to the rapid development in information technology, various display devices have evolved into instruments that can process and display a great deal of information. Flat panel display (FPD) devices, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), vacuum fluorescent display (VFD) devices, and electroluminescent display (ELD) devices, have been developed.
Among these devices, liquid crystal display (LCD) devices are most widely used in place of cathode ray tubes (CRTs) due to their lightweight, thin thickness and low power consumption. The LCD devices are used not only for potable devices such as monitors of notebook computers but also for televisions and monitors of personal computers.
An LCD device includes thin film transistors as switching elements. In general, silicon is used as an active layer of the thin film transistor.
Recently, polyacetylene, which is a conjugated organic polymer having semiconductor properties, has been developed. Organic semiconductors have been researched as new electrical and electronic materials in a wide range of functional electronic devices, optical devices, etc. due to various synthesizing methods, ease to form thin films, flexibility, conductivity, and low production costs. Organic thin film transistors (OTFTs), which have substantially the same structure as silicon thin film transistors (Si-TFTs) and include an organic material as an active layer, have been researched and developed.
FIG. 1 is a plane view of an array substrate for an organic thin film transistor (OTFT) liquid crystal display (LCD) device according to the related art. In FIG. 1, gate lines 20 are formed along a direction on a substrate 10, and a gate pad 40 is disposed at one end of each of the gate lines 20. Data lines 30 cross the gate lines 20 to define pixel regions P, and a data pad 50 is disposed at one end of each of the data lines 30.
An organic thin film transistor OT is formed at each crossing point of the gate lines 20 and the data lines 30. The organic thin film transistor OT includes a source electrode 32 that extends from the data line 30, a drain electrode 34 that is spaced apart from the source electrode 32, a gate electrode 36 that extends from the gate line 20 over the source and drain electrodes 32 and 34, and an organic semiconductor layer (not shown) that is disposed between the gate electrode 36 and each of the source electrode 32 and the drain electrode 34.
A pixel electrode 70 is formed in the pixel region P. The pixel electrode 70 directly contacts the drain electrode 34 and is spaced apart from the gate line 20, the data line 30, and the organic thin film transistor OT, particularly, the gate electrode 36 and the source electrode 32.
Hereinafter, a method of manufacturing an array substrate for an OTFT LCD device according to the related art will be described with reference to accompanying drawings.
FIGS. 2A to 2F, FIGS. 3A to 3F, and FIGS. 4A to 4F illustrate a method of manufacturing an array substrate for an OTFT LCD device according to the related art. FIGS. 2A to 2F are cross-sectional views along the line II-II of FIG. 1, FIGS. 3A to 3F are cross-sectional views along the line III-III of FIG. 1, and FIGS. 4A to 4F are cross-sectional views along the line IV-IV of FIG. 1.
In FIG. 2A, FIG. 3A and FIG. 4A, a switching region S, a pixel region P, a gate region G, and a data region D are defined on a substrate 10.
A metallic material is deposited on the substrate 10 where the regions S, P, G and D are defined and then is patterned to thereby form a source electrode 32, a drain electrode 34, and a data line 30 of FIG. 1. The source and drain electrodes 32 and 34 correspond to the switching region S. The data line 30 corresponds to the data region D and has a data pad 50 at one end thereof. The metallic material may be one or more selected from a conductive metallic group including aluminum (Al), aluminum alloy such as aluminum neodymium (AlNd), molybdenum (Mo), tungsten (W), and chromium (Cr).
In FIG. 2B, FIG. 3B and FIG. 4B, a transparent conductive material is deposited on the substrate 10 including the source and drain electrodes 32 and 34 and then is patterned to thereby form a pixel electrode 70 and a data pad terminal 52. The pixel electrode 70 directly contacts a part of the drain electrode 34. The data pad terminal 52 is disposed in the data region D and contacts the data pad 50. The transparent conductive material may be one of indium tin oxide (ITO) and indium zinc oxide (IZO).
In FIG. 2C, FIG. 3C and FIG. 4C, a low molecular organic material layer 45a is formed substantially on an entire surface of the substrate 10 including the pixel electrode 70 by applying one selected from a low molecular organic material group. Subsequently, an organic insulating layer 55a is formed on the low molecular organic material layer 45a. 
In FIG. 2D, FIG. 3D and FIG. 4D, the low molecular organic material layer 45a and the organic insulating layer 55a are patterned to thereby form an organic semiconductor layer 45 and a gate insulating layer 55 in the switching region S. The organic semiconductor layer 45 and the gate insulating layer 55 thereon have the same width.
The source and drain electrodes 32 and 34 are spaced apart from each other. The organic semiconductor layer 45 and the gate insulating layer 55 overlap the source and drain electrodes 32 and 34.
In FIG. 2E, FIG. 3E and FIG. 4E, a metallic material is deposited substantially on an entire surface of the substrate 10 including the organic semiconductor layer 45 and the gate insulating layer 55 and then is patterned to thereby form a gate electrode 36, a gate line 20 of FIG. 1 and a gate pad 40. The gate electrode 36 is disposed on the gate insulating layer 55 and has the same width with the gate insulating layer 55. The gate line 20 is disposed in the gate region G and is connected to the gate electrode 36. The gate pad 40 is disposed at one end of the gate line 20. The gate pad 40 is part of the gate line 20 and is electrically connected to the gate line 20. The metallic material may be selected from a metallic material group including aluminum (Al), aluminum alloy such as aluminum neodymium (AlNd), molybdenum (Mo), tungsten (W) and chromium (Cr).
In FIG. 2F, FIG. 3F and FIG. 4F, a passivation layer 60 is formed substantially on an entire surface of the substrate 10. The passivation layer 60 may be one or more selected from an organic insulating material group. The passivation layer 60 is patterned to thereby form a gate pad contact hole CH1, a data pad contact hole CH2, and a pixel opening OH. The gate pad contact hole CH1 partially exposes the gate pad 40. The data pad contact hole CH2 partially exposes the data pad terminal 52. The pixel opening OH exposes the pixel electrode 70.
An array substrate according to the related art may be manufactured through the above-mentioned processes.
In an LCD device including the array substrate having an organic TFT of a top gate type, in which the gate electrode 36 is disposed over the source and drain electrodes 32 and 34, the gate pad 40 is formed of the same material as the gate electrode 36, i.e., one selected from a conductive metallic group, and there may be problems when a gate driver is connected to the gate pad according to a TAB (tape automated bonding) package method. That is, when the gate driver is connected to the gate pad, misalignment may occur. To connect the gate driver to the gate pad again, when the gate driver is detached from the gate pad, the gate pad is torn off. Additionally, the gate pad is exposed to atmospheric conditions, and thus the gate pad is corroded.